module u13dumb title 'DRAM Controller' "This PAL generates RAS and WE signals for the DRAM modules and controls "refresh operations. "Change MEM_SIZE here to correct memory size in Megabytes: MEM_SIZE = 16; *Choices are: 4, 8, 16, 32, 64, 128 @IF (MEM_SIZE == 4) {u13_4m device 'mach220a';} @IF (MEM_SIZE == 8) {u13_8m device 'mach220a';} @IF (MEM_SIZE == 16) {u13_16m device 'mach220a';} @IF (MEM_SIZE == 32) {u13_32m device 'mach220a';} @IF (MEM_SIZE == 64) {u13_64m device 'mach220a';} @IF (MEM_SIZE == 128) {u13_128m device 'mach220a';} "Inputs CLK,RESET,MADS,DRAMSEL,NBAEN,REFREQ pin 15,51,50,17,54,3; CWR,NBRD,NENE pin 37,36,20; LCDTS pin 62; MCACHE,MKEN,LLEN pin 10,16,49; LCACHE pin 63; MA3,MA4,MA22,MA24,MA26 pin 29,30,31,32,33; PD1,PD2,PD3,PD4,PD5 pin 12,14,65,67,6; " BURST12 pin 47; "Outputs RREFREQ pin; EARLY pin 55; " TOP node; " DUALBANK node; " LAST node; BURST1P node; BURST2 node; BURST4 node; CNT0,CNT1,CNT2 node istype 'reg_t,buffer'; DSB0,DSB1,DSB2,DSB3,DSB4 node istype 'reg_d'; ROWEN,COLEN,GOCASA,GOCASB pin 21,22,56,13; CBRREF,DRDY,MA4B pin 57,59,60; WEA1,WEA2,WEB1,WEB2 pin 26,25,24,23; RASLA1,RASLA2,RASHA1,RASHA2 pin 7,5,4,2; RASLB1,RASLB2,RASHB1,RASHB2 pin 43,45,46,48; C,L,H,Z,X = .C.,0,1,.Z.,.X.; " AMDMACH property 'GROUP F RASLB1 RASLB2 RASHB1 RASHB2'; " AMDMACH property 'GROUP C WEA1 WEA2 WEB1 WEB2' RASLA = [RASLA1,RASLA2]; RASLB = [RASLB1,RASLB2]; RASHA = [RASHA1,RASHA2]; RASHB = [RASHB1,RASHB2]; RASL = [RASLA1,RASLA2,RASLB1,RASLB2]; RASH = [RASHA1,RASHA2,RASHB1,RASHB2]; RAS = [RASLA1,RASLA2,RASLB1,RASLB2,RASHA1,RASHA2,RASHB1,RASHB2]; WE = [WEA1,WEA2,WEB1,WEB2]; " WE = [WEA1,WEB1]; " WE2 = [WEA2,WEB2]; RCNT = [CNT2,CNT1,CNT0]; DSTATE = [DSB4..DSB0]; S0 = ^b00000; S24 = ^b10110; S1 = ^b01000; S2 = ^b01001; S3 = ^b01011; S4 = ^b01010; S5 = ^b01110; S6 = ^b01100; S7 = ^b01101; S8 = ^b01111; S9 = ^b00100; S21 = ^b00101; S22 = ^b00111; S23 = ^b00010; S10 = ^b00011; S11 = ^b10010; S12 = ^b10011; S13 = ^b11011; S14 = ^b11010; S15 = ^b11110; S16 = ^b11100; S17 = ^b11101; S18 = ^b11111; S19 = ^b10111; S20 = ^b10101; S25 = ^b10100; S26 = ^b10000; S27 = ^b00001; S28 = ^b11000; S29 = ^b10001; S30 = ^b00110; S31 = ^b11001; " M512K = PD1 & !PD2 & PD5; Use this for 'smart' memory controller " M2M = PD1 & PD2 & PD5; " M8M = PD1 & PD2 & !PD5; " M512K = 0; Comment out above declarations or use these to 'fix' memory size " M2M = 0; " M8M = 0; @IF (MEM_SIZE == 4) { BOTTOM = MA22 & MA24 & MA26 "decode top 4M # !MA22 & !MA24 & !MA26; "and bottom 4M TOP = 0; } @IF (MEM_SIZE == 8) { BOTTOM = !MA22 & MA24 & MA26 "decode top 8M # !MA22 & !MA24 & !MA26; "and bottom 8M TOP = MA22 & MA24 & MA26 # MA22 & !MA24 & !MA26; } @IF (MEM_SIZE == 16) { BOTTOM = MA24 & MA26 # !MA24 & !MA26; TOP = 0; } @IF (MEM_SIZE == 32) { BOTTOM = !MA24 & MA26 # !MA24 & !MA26; TOP = MA24 & MA26 # MA24 & !MA26; } @IF (MEM_SIZE == 64) { BOTTOM = 1; TOP = 0; } @IF (MEM_SIZE == 128) { BOTTOM = !MA26; TOP = MA26; } DUALBANK = (MEM_SIZE == 8) # (MEM_SIZE == 32) # (MEM_SIZE == 128); " BOTTOM = M512K & !MA22 " # M2M & !MA24 " # M8M & !MA26; BURST1 = NBAEN & !LLEN & !CWR & (MCACHE # MKEN) # NBAEN & !LLEN & CWR & MCACHE # !NBAEN; LAST = 1; equations LCDTS = PD1 & PD2 & PD3 & PD4 & PD5; "Dummy equation to make PD[1:5] inputs!!! LCDTS.OE=0; MA22.OE=0; MA24.OE=0; MA26.OE=0; " TOP = M512K & MA22 " # M2M & MA24 " # M8M & MA26; BURST1P = BURST1; BURST2 = NBAEN & LLEN & !CWR & (MCACHE # MKEN) # NBAEN & LLEN & CWR & MCACHE; BURST4 = NBAEN & !MCACHE & CWR # NBAEN & !MCACHE & !CWR & !MKEN; DSTATE.clk = CLK; !RREFREQ := RESET & !REFREQ # RESET & !RREFREQ & !CBRREF; RREFREQ.clk = CLK; CBRREF := RESET & (DSTATE == S0) & !RREFREQ # RESET & (DSTATE == S1) # RESET & (DSTATE == S2) # RESET & (DSTATE == S3) # RESET & (DSTATE == S4) # RESET & (DSTATE == S5) # RESET & (DSTATE == S6) # RESET & (DSTATE == S7) # RESET & (DSTATE == S8) & !LAST; CBRREF.clk = CLK; MA4B := MA4 & (DSTATE == S0) # MA4 & (DSTATE == S24) # MA4 & (DSTATE == S9) # MA4 & (DSTATE == S21) # MA4 & (DSTATE == S22) # MA4 & (DSTATE == S10) # MA4 & (DSTATE == S11) # MA4 & (DSTATE == S12) # MA4 & (DSTATE == S13) # !MA4 & (DSTATE == S14) # !MA4 & (DSTATE == S15) # !MA4 & (DSTATE == S16) # !MA4 & (DSTATE == S17) # !MA4 & (DSTATE == S18) # !MA4 & (DSTATE == S19) # !MA4 & (DSTATE == S20); MA4B.clk = CLK; !ROWEN := RESET & (DSTATE == S0) # RESET & (DSTATE == S9) "Page Miss or Nubus Transfer # RESET & (DSTATE == S21); ROWEN.clk = CLK; COLEN := RESET & (DSTATE == S0) # RESET & (DSTATE == S9) # RESET & (DSTATE == S21); COLEN.clk = CLK; !WE := RESET & RREFREQ & !MADS & !DRAMSEL & (DSTATE == S0) & NBAEN & CWR # RESET & RREFREQ & !MADS & !DRAMSEL & (DSTATE == S24) & NBAEN & CWR & !NENE # RESET & RREFREQ & !MADS & !DRAMSEL & (DSTATE == S0) & !NBAEN & NBRD # RESET & !WE & !MADS & !(DSTATE == S20); WE.clk = CLK; RASL := !RESET # (DSTATE == S0) # (DSTATE == S24) & !RREFREQ # (DSTATE == S24) & !MADS & !DRAMSEL & (NENE # !NBAEN) # (DSTATE == S1) # (DSTATE == S6) # (DSTATE == S7) # (DSTATE == S8) # (DSTATE == S9) # (DSTATE == S12) & !NBAEN # RASL & !CBRREF & !((DSTATE == S21) & BOTTOM); RASL.clk = CLK; RASH := !RESET # (DSTATE == S0) # (DSTATE == S24) & !RREFREQ # (DSTATE == S24) & !MADS & !DRAMSEL & (NENE # !NBAEN) # (DSTATE == S1) # (DSTATE == S6) # (DSTATE == S7) # (DSTATE == S8) # (DSTATE == S9) # (DSTATE == S12) & !NBAEN # RASH & !CBRREF & !((DSTATE == S21) & TOP) # !DUALBANK; RASH.clk = CLK; GOCASA := RESET & (DSTATE == S0) & !RREFREQ # RESET & (DSTATE == S1) # RESET & (DSTATE == S2) # RESET & (DSTATE == S22) & MA3 & WEA1 # RESET & (DSTATE == S10) & !MA3 # RESET & (DSTATE == S11) & MA3 & !BURST1P & WEA1 # RESET & (DSTATE == S12) & MA3 & !BURST1P # RESET & (DSTATE == S14) & !MA3 & !BURST2 & WEA1 # RESET & (DSTATE == S15) & !MA3 & !BURST2 # RESET & (DSTATE == S16) & MA3 & WEA1 # RESET & (DSTATE == S17) & MA3 # RESET & (DSTATE == S24) & !MA3 & !MADS & !DRAMSEL & RREFREQ & !NENE & NBAEN; GOCASA.clk = CLK; GOCASB := RESET & (DSTATE == S0) & !RREFREQ # RESET & (DSTATE == S1) # RESET & (DSTATE == S2) # RESET & (DSTATE == S22) & MA3 & WEA1 # RESET & (DSTATE == S10) & MA3 # RESET & (DSTATE == S11) & !MA3 & !BURST1P & WEA1 # RESET & (DSTATE == S12) & !MA3 & !BURST1P # RESET & (DSTATE == S14) & MA3 & !BURST2 & WEA1 # RESET & (DSTATE == S15) & MA3 & !BURST2 # RESET & (DSTATE == S16) & !MA3 & WEA1 # RESET & (DSTATE == S17) & !MA3 # RESET & (DSTATE == S24) & MA3 & !MADS & !DRAMSEL & RREFREQ & !NENE & NBAEN; GOCASB.clk = CLK; !DRDY := RESET & (DSTATE == S24) & !MADS & !DRAMSEL & !NENE & NBAEN & CWR & RREFREQ # RESET & (DSTATE == S10) # RESET & (DSTATE == S12) & !BURST1 # RESET & (DSTATE == S15) & !BURST2 # RESET & (DSTATE == S17); DRDY.clk = CLK; CNT0.T = (DSTATE == S4); CNT1.T = (DSTATE == S4) & CNT0; CNT2.T = (DSTATE == S4) & CNT0 & CNT1; RCNT.AR = (DSTATE == S1); RCNT.clk = CLK; !EARLY := RESET & !MADS & !DRAMSEL & !NBAEN & (DSTATE == S22); EARLY.clk = CLK; state_diagram DSTATE State S0: "RAS precharge state for new accesses; S24 is idle state for page mode IF RESET & !RREFREQ THEN S1 ELSE IF !MADS & !DRAMSEL THEN S9 ELSE S0; State S24: "Idle State for page mode access, RAS lines are asserted IF !RESET THEN S0 ELSE IF !RREFREQ THEN S0 ELSE IF !MADS & !DRAMSEL & (NENE # !NBAEN) THEN S0 ELSE IF !MADS & !DRAMSEL & !NENE & NBAEN & !CWR THEN S10 ELSE IF !MADS & !DRAMSEL & !NENE & NBAEN & CWR THEN S11 ELSE S24; "RAS Precharge States State S9: "RAS Precharge 2 IF !RESET THEN S0 ELSE S21; State S21: "RAS Precharge 3 IF !RESET THEN S0 ELSE S22; State S22: "Assert RAS IF !RESET THEN S0 ELSE S10; "CAS States, Start here for Page Hits State S10: "Switch to Column Address IF !RESET THEN S0 ELSE S11; State S11: "CAS0, DRDY Asserted IF !RESET THEN S0 ELSE S12; State S12: "CAS0 Hold, MBRDY Asserted IF !RESET THEN S0 ELSE IF !NBAEN THEN S0 ELSE IF BURST1 THEN S20 ELSE S13; State S13: "CAS1, DRDY Asserted IF !RESET THEN S0 ELSE S14; State S14: "CAS1 Hold, MBRDY Asserted IF !RESET THEN S0 ELSE IF BURST2 THEN S20 ELSE S15; State S15: "Toggle MA4B for burst accesses IF !RESET THEN S0 ELSE S16; State S16: "CAS2, DRDY Asserted IF !RESET THEN S0 ELSE S17; State S17: "CAS2 Hold, MBRDY Asserted IF !RESET THEN S0 ELSE S18 State S18: "CAS3, DRDY Asserted IF !RESET THEN S0 ELSE S19; State S19: "CAS3 Hold, MBRDY Asserted IF !RESET THEN S0 ELSE S20; State S20: "Done IF !RESET THEN S0 ELSE S24; " ELSE IF !RREFREQ THEN S0 " ELSE IF MADS THEN S24 " ELSE S20; "Refresh States State S1: "Refresh, Load Refresh Counter IF !RESET THEN S0 ELSE S2; State S2: "Refresh State 1 IF !RESET THEN S0 ELSE S3; State S3: "Refresh State 2 IF !RESET THEN S0 ELSE S4; State S4: "Refresh State 3 IF !RESET THEN S0 ELSE S5; State S5: "Refresh State 4 IF !RESET THEN S0 ELSE S6; State S6: "Refresh State 5 IF !RESET THEN S0 ELSE S7; State S7: "Refresh State 6 IF !RESET THEN S0 ELSE S8; State S8: "Refresh State 7 IF !RESET # LAST THEN S0 ELSE S2; "Unused States State S23: GOTO S0; State S25: GOTO S0; State S26: GOTO S0; State S27: GOTO S0; State S28: GOTO S0; State S29: GOTO S0; State S30: GOTO S0; State S31: GOTO S0; test_vectors ([CLK,RESET,!REFREQ,MADS,DRAMSEL,PD1,PD2] -> [DSTATE,!RREFREQ,RCNT,CBRREF,RAS,GOCASA,GOCASB]) "1. Refresh [C,0,X,1,1,1,1] -> [S0,0,X,0,^b11111111,0,0]; "Reset [C,1,0,1,1,1,1] -> [S0,0,X,0,^b11111111,0,0]; "Do Nothing [C,1,1,1,1,1,1] -> [S0,1,X,0,^b11111111,0,0]; "Do Nothing, Wait for !RREFREQ [C,1,1,1,1,1,1] -> [S1,1,X,1,^b11111111,1,1]; "Refresh State, reset RCNT "5. Refresh [C,1,0,1,1,1,1] -> [S2,0,X,1,^b11111111,1,1]; "Refresh State 1 @IF (DUALBANK) { [C,1,0,1,1,1,1] -> [S3,0,X,1,^b00000000,1,1]; "Refresh State 2 [C,1,0,1,1,1,1] -> [S4,0,X,1,^b00000000,0,0]; "Refresh State 3 [C,1,0,1,1,1,1] -> [S5,0,X,1,^b00000000,0,0]; "Refresh State 4 [C,1,0,1,1,1,1] -> [S6,0,X,1,^b00000000,0,0]; "Refresh State 5 } @IF (!DUALBANK) { [C,1,0,1,1,1,1] -> [S3,0,X,1,^b00001111,1,1]; "Refresh State 2 [C,1,0,1,1,1,1] -> [S4,0,X,1,^b00001111,0,0]; "Refresh State 3 [C,1,0,1,1,1,1] -> [S5,0,X,1,^b00001111,0,0]; "Refresh State 4 [C,1,0,1,1,1,1] -> [S6,0,X,1,^b00001111,0,0]; "Refresh State 5 } [C,1,0,1,1,1,1] -> [S7,0,X,1,^b11111111,0,0]; "Refresh State 6 [C,1,0,1,1,1,1] -> [S8,0,X,1,^b11111111,0,0]; "Refresh State 7 [C,1,0,1,1,1,1] -> [S0,0,X,0,^b11111111,0,0]; "Back to S0 test_vectors ([CLK,RESER,!REFREQ,MADS,DRAMSEL,NBAEN,CWR,NBRD,LCDTS,NENE,MCACHE,MKEN,LCACHE,LLEN, MA3,MA4,MA22,MA24,MA26,PD1,PD2,PD5] -> [DSTATE,DRDY,!RREFREQ,RCNT,CBRREF,WE,ROWEN,COLEN,MA4B,RAS,GOCASA,GOCASB]) " C R R M D N C N L N M M L L M M M M M P P P -> D D R R C W R C M R G G " L E E A R B W B C E C K C L A A A A A D D D S R R C B E O O A A O O " K S F D A A R R D N A E A E 3 4 2 2 2 1 2 5 T D E N R W L 4 S C C " E R S M E D T E C N C N 2 4 6 A Y F T R E E B A A " T E S N S H H T R E N N S S " Q E E E E E F A B "13. DRAM cycles from S0 [C,1,0,1,X,X,X,X,X,X,X,X,X,X,X,0,X,X,X,X,X,X] -> [ S0,1,0,X,0,^b1111,0,1,0,^b11111111,0,0]; "Do Nothing [C,1,0,1,X,X,X,X,X,X,X,X,X,X,X,1,X,X,X,X,X,X] -> [ S0,1,0,X,0,^b1111,0,1,1,^b11111111,0,0]; "Do Nothing [C,1,0,0,1,X,X,X,X,X,X,X,X,X,X,0,X,X,X,X,X,X] -> [ S0,1,0,X,0,^b1111,0,1,0,^b11111111,0,0]; "Do Nothing [C,1,0,1,0,X,X,X,X,X,X,X,X,X,X,0,X,X,X,X,X,X] -> [ S0,1,0,X,0,^b1111,0,1,0,^b11111111,0,0]; "Do Nothing "17. Cache Write, Burst of 4, Starting Offset = 0 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [ S9,1,0,X,0,^b0000,0,1,0,^b11111111,0,0]; "RAS Precharge 2 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S21,1,0,X,0,^b0000,0,1,0,^b11111111,0,0]; "RAS Precharge 3 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S22,1,0,X,0,^b0000,0,1,0,^b00001111,0,0]; "Assert RASL [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S10,1,0,X,0,^b0000,1,0,0,^b00001111,0,0]; "Switch Address [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S11,0,0,X,0,^b0000,1,0,0,^b00001111,1,0]; "Wait for valid data [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S12,1,0,X,0,^b0000,1,0,0,^b00001111,0,0]; "CAS0 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S13,0,0,X,0,^b0000,1,0,0,^b00001111,0,1]; "Wait for valid data [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S14,1,0,X,0,^b0000,1,0,0,^b00001111,0,0]; "CAS1 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S15,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "MA4B [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S16,0,0,X,0,^b0000,1,0,1,^b00001111,1,0]; "Wait for valid data [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S17,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "CAS2 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S18,0,0,X,0,^b0000,1,0,1,^b00001111,0,1]; "Wait for valid data [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S19,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "CAS3 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S20,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "Done [C,1,0,1,0,1,X,X,X,X,X,X,X,X,0,0,0,0,0,X,X,X] -> [S24,1,0,X,0,^b1111,1,0,1,^b00001111,0,0]; "Idle State [C,1,0,1,0,1,X,X,X,X,X,X,X,X,0,0,0,0,0,X,X,X] -> [S24,1,0,X,0,^b1111,1,0,0,^b00001111,0,0]; "Idle State "32. Cache Read, Burst of 4, Starting Offset = 0, NENE=0 [C,1,0,0,0,1,0,X,1,0,0,0,X,X,0,0,0,0,0,X,X,X] -> [S10,1,0,X,0,^b1111,1,0,0,^b00001111,1,0]; "Switch Address [C,1,0,0,0,1,0,X,1,0,0,0,X,X,0,0,0,0,0,X,X,X] -> [S11,0,0,X,0,^b1111,1,0,0,^b00001111,1,0]; "CAS0 [C,1,0,0,0,1,0,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S12,1,0,X,0,^b1111,1,0,0,^b00001111,0,1]; "CAS0 [C,1,0,0,0,1,0,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S13,0,0,X,0,^b1111,1,0,0,^b00001111,0,1]; "CAS1 [C,1,0,0,0,1,0,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S14,1,0,X,0,^b1111,1,0,0,^b00001111,0,0]; "CAS1 [C,1,0,0,0,1,0,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S15,1,0,X,0,^b1111,1,0,1,^b00001111,1,0]; "MA4B [C,1,0,0,0,1,0,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S16,0,0,X,0,^b1111,1,0,1,^b00001111,1,0]; "CAS2 [C,1,0,0,0,1,0,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S17,1,0,X,0,^b1111,1,0,1,^b00001111,0,1]; "CAS2 [C,1,0,0,0,1,0,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S18,0,0,X,0,^b1111,1,0,1,^b00001111,0,1]; "CAS3 [C,1,0,0,0,1,0,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S19,1,0,X,0,^b1111,1,0,1,^b00001111,0,0]; "CAS3 [C,1,0,0,0,1,0,X,1,X,0,0,X,X,0,0,0,0,0,X,X,X] -> [S20,1,0,X,0,^b1111,1,0,1,^b00001111,0,0]; "Done [C,1,0,1,0,1,X,X,X,X,X,X,X,X,0,0,0,0,0,X,X,X] -> [S24,1,0,X,0,^b1111,1,0,1,^b00001111,0,0]; "Idle State [C,1,0,1,0,1,X,X,X,X,X,X,X,X,0,0,0,0,0,X,X,X] -> [S24,1,0,X,0,^b1111,1,0,0,^b00001111,0,0]; "Idle State "44. Cache Write, Burst of 4, Starting Offset = 18, NENE=0 [C,1,0,0,0,1,1,X,1,0,0,0,X,X,1,1,0,0,0,X,X,X] -> [S11,0,0,X,0,^b0000,1,0,1,^b00001111,0,1]; "Wait for valid data [C,1,0,0,0,1,1,X,1,X,0,0,X,X,1,1,0,0,0,X,X,X] -> [S12,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "CAS3 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,1,1,0,0,0,X,X,X] -> [S13,0,0,X,0,^b0000,1,0,1,^b00001111,1,0]; "Wait for valid data [C,1,0,0,0,1,1,X,1,X,0,0,X,X,1,1,0,0,0,X,X,X] -> [S14,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "CAS2 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,1,1,0,0,0,X,X,X] -> [S15,1,0,X,0,^b0000,1,0,0,^b00001111,0,0]; "MA4B [C,1,0,0,0,1,1,X,1,X,0,0,X,X,1,1,0,0,0,X,X,X] -> [S16,0,0,X,0,^b0000,1,0,0,^b00001111,0,1]; "Wait for valid data [C,1,0,0,0,1,1,X,1,X,0,0,X,X,1,1,0,0,0,X,X,X] -> [S17,1,0,X,0,^b0000,1,0,0,^b00001111,0,0]; "CAS1 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,1,1,0,0,0,X,X,X] -> [S18,0,0,X,0,^b0000,1,0,0,^b00001111,1,0]; "Wait for valid data [C,1,0,0,0,1,1,X,1,X,0,0,X,X,1,1,0,0,0,X,X,X] -> [S19,1,0,X,0,^b0000,1,0,0,^b00001111,0,0]; "CAS0 [C,1,0,0,0,1,1,X,1,X,0,0,X,X,1,1,0,0,0,X,X,X] -> [S20,1,0,X,0,^b0000,1,0,0,^b00001111,0,0]; "Done [C,1,0,1,0,1,X,X,X,X,X,X,X,X,1,1,0,0,0,X,X,X] -> [S24,1,0,X,0,^b1111,1,0,0,^b00001111,0,0]; "Idle State [C,1,0,1,0,1,X,X,X,X,X,X,X,X,0,0,0,0,0,X,X,X] -> [S24,1,0,X,0,^b1111,1,0,0,^b00001111,0,0]; "Idle State "55. Cache Write, Single Transfer, Starting Offset = 10, NENE=0 [C,1,0,0,0,1,1,X,1,0,1,0,1,0,0,1,0,0,0,X,X,X] -> [S11,0,0,X,0,^b0000,1,0,1,^b00001111,1,0]; "Wait for valid data [C,1,0,0,0,1,1,X,1,X,1,0,1,0,0,1,0,0,0,X,X,X] -> [S12,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "CAS0 [C,1,0,0,0,1,1,X,1,X,1,0,1,0,0,1,0,0,0,X,X,X] -> [S20,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "Done [C,1,0,1,0,1,X,X,X,X,X,X,1,0,0,1,0,0,0,X,X,X] -> [S24,1,0,X,0,^b1111,1,0,0,^b00001111,0,0]; "Idle State [C,1,0,1,0,1,X,X,X,X,X,X,1,0,0,0,0,0,0,X,X,X] -> [S24,1,0,X,0,^b1111,1,0,0,^b00001111,0,0]; "Idle State " C R R M D N C N L N M M L L M M M M M P P P -> D D R R C W R C M R G G " L E E A R B W B C E C K C L A A A A A D D D S R R C B E O O A A O O " K S F D A A R R D N A E A E 3 4 2 2 2 1 2 5 T D E N R W L 4 S C C " E R S M E D T E C N C N 2 4 6 A Y F T R E E B A A " T E S N S H H T R E N N S S " Q E E E E E F A B "60. NuBus Read [C,1,0,0,0,0,X,0,1,X,X,X,X,X,1,0,0,0,0,X,X,X] -> [ S0,1,0,X,0,^b1111,1,0,0,^b11111111,0,0]; "NuBus Transfer [C,1,0,0,0,0,X,0,1,X,X,X,X,X,1,0,0,0,0,X,X,X] -> [ S9,1,0,X,0,^b1111,0,1,0,^b11111111,0,0]; "RAS Precharge 2 [C,1,0,0,0,0,X,0,1,X,X,X,X,X,1,0,0,0,0,X,X,X] -> [S21,1,0,X,0,^b1111,0,1,0,^b11111111,0,0]; "RAS Precharge 3 [C,1,0,0,0,0,X,0,1,X,X,X,X,X,1,0,0,0,0,X,X,X] -> [S22,1,0,X,0,^b1111,0,1,0,^b00001111,0,0]; "Assert RASL [C,1,0,0,0,0,X,0,1,X,X,X,X,X,1,0,0,0,0,X,X,X] -> [S10,1,0,X,0,^b1111,1,0,0,^b00001111,0,1]; "Switch Address [C,1,0,0,0,0,X,0,1,X,X,X,X,X,1,0,0,0,0,X,X,X] -> [S11,0,0,X,0,^b1111,1,0,0,^b00001111,0,1]; "CAS0 [C,1,0,0,0,0,X,0,1,X,X,X,X,X,1,0,0,0,0,X,X,X] -> [S12,1,0,X,0,^b1111,1,0,0,^b00001111,0,0]; "Hold [C,1,0,0,0,0,X,1,1,X,X,X,X,X,1,0,0,0,0,X,X,X] -> [ S0,1,0,X,0,^b1111,1,0,0,^b11111111,0,0]; "Back to S0 [C,1,0,1,0,1,X,1,1,X,X,X,X,X,1,0,0,0,0,X,X,X] -> [ S0,1,0,X,0,^b1111,0,1,0,^b11111111,0,0]; "Stay in S0 "69. NuBus Write [C,1,0,0,0,0,X,1,1,X,X,X,X,X,1,1,0,0,0,X,X,X] -> [ S9,1,0,X,0,^b0000,0,1,1,^b11111111,0,0]; "RAS Precharge 2 [C,1,0,0,0,0,X,1,1,X,X,X,X,X,1,1,0,0,0,X,X,X] -> [S21,1,0,X,0,^b0000,0,1,1,^b11111111,0,0]; "RAS Precharge 3 [C,1,0,0,0,0,X,1,1,X,X,X,X,X,1,1,0,0,0,X,X,X] -> [S22,1,0,X,0,^b0000,0,1,1,^b00001111,0,0]; "Assert RASL [C,1,0,0,0,0,X,1,1,X,X,X,X,X,1,1,0,0,0,X,X,X] -> [S10,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "Switch Address [C,1,0,0,0,0,X,1,1,X,X,X,X,X,1,1,0,0,0,X,X,X] -> [S11,0,0,X,0,^b0000,1,0,1,^b00001111,0,1]; "CAS0 [C,1,0,0,0,0,X,1,1,X,X,X,X,X,1,1,0,0,0,X,X,X] -> [S12,1,0,X,0,^b0000,1,0,1,^b00001111,0,0]; "Hold [C,1,0,0,0,0,X,1,1,X,X,X,X,X,1,1,0,0,0,X,X,X] -> [ S0,1,0,X,0,^b0000,1,0,1,^b11111111,0,0]; "Back to S0 [C,1,0,1,0,1,X,1,1,X,X,X,X,X,1,1,0,0,0,X,X,X] -> [ S0,1,0,X,0,^b1111,0,1,1,^b11111111,0,0]; "Stay in S0 test_vectors ([NBAEN,MKEN,MCACHE,LCACHE,CWR,LLEN] -> [BURST1P,BURST2,BURST4]) "77. BURST signal generation [0,X,X,X,X,X] -> [1,0,0]; [1,1,X,X,X,X] -> [1,0,0]; [1,0,0,0,0,0] -> [0,0,1]; [1,0,0,0,0,1] -> [0,0,1]; [1,0,0,0,1,0] -> [0,0,1]; [1,0,0,0,1,1] -> [0,0,1]; [1,0,0,1,0,0] -> [0,0,1]; [1,0,0,1,0,1] -> [0,0,1]; [1,0,0,1,1,0] -> [0,0,1]; [1,0,0,1,1,1] -> [0,0,1]; [1,0,1,0,0,0] -> [1,0,0]; [1,0,1,0,0,1] -> [0,1,0]; [1,0,1,0,1,0] -> [1,0,0]; [1,0,1,0,1,1] -> [0,1,0]; [1,0,1,1,0,0] -> [1,0,0]; [1,0,1,1,0,1] -> [0,1,0]; [1,0,1,1,1,0] -> [1,0,0]; [1,0,1,1,1,1] -> [0,1,0]; end